The reconstruction error is a maximum of 3 A for both high and low currents. This is promising for applications with intended switching frequencies above 10 kHz and are within the silicon carbide (SiC) MOSFET domain. The absolute error of the RSCS for both high and low currents is a maximum of 3 A for frequen-cies above 10 kHz. The delay between the reconstructed phase current and the current in the system is 1.61 μs.
#Mosfet coil driver circuit driver
The gate driver is able to successfully reconstruct the phase current under a dv/dt of 15 V/ns. A 2.5 Msps DAC with a small settling time, is chosen to convert information back to analog, without minimizing delay. Immediately after successful subtraction, the FPGA starts placing that information on the digital-to-analog converter (DAC). Two ADCs for the top and bottom switch currents are synchronized and send data in the field-programmable gate array (FPGA) at the same time instances. The chosen sample rate of the ADC is 2.5 MHz in order to reduce delay of the current measurement. The OpAmp level shifter is employed to adjust the signal to the proper values for ADC sampling. Its main role is to filter out any high frequency ringing in the current information during switching instances. After buffer, there is a two-stage analog-to-digital converter (ADC) filter with a cutoff frequency of 3.3 MHz. The output voltage of an integrator linearly represents current in the system. The di/dt information, scaled with a factor of mutual inductance, is being con-stantly integrated by an active integrator. A digital reconstruction of the phase current is chosen, as shown in Fig. The chosen GD architecture is one where an RSCS for the top and bottom device is placed on the controller (common) ground.
Outputting the phase current from the GD is possible by knowing the switch currents in the complete switching cycle and simply subtracting these two currents.
In the newly designed GD, switch currents are measured and used for protection, while the same information is used for obtaining the phase current with a simple manipulation on the GD itself (shown on Fig. Gate Driver PrototypeThe necessity of having a new, fast, and reliable short-circuit protection method for SiC applications, and the emergence of high density, high efficiency trends, drove the introduction of the gate driver (GD) with an integrated Rogowski switch-current sensor (RSCS). Global Intergrid for Sustainable Energy Abundanceįig.
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